1. Field of the Invention
The present invention relates to a dynamic barrel shifter of a pre-charge method, and particularly to a dynamic barrel shifter of low power consumption capable of high speed operation.
2. Description of the Background Art
A dynamic barrel shifter which can receive data in parallel, freely shift the data in a predetermined direction by a predetermined number of bits, and output it in parallel has been employed in a high level microprocessor.
FIG. 1 shows an example of construction of a conventional four-bit dynamic barrel shifter.
As shown in the drawing, the four-bit dynamic barrel shifter 1 includes clocked inverters 2a to 2d for receiving binary codes D0 to D3 forming four-bit data, a first selector portion 3 for selecting whether the data is shifted by two bits to the left direction defined at the drawing after the data is inverted and driven by the clocked inverters 2a to 2d and outputted in parallel, a pre-charge circuit 4 for carrying out pre-charge synchronized with a clock signal to nodes N1 to N6 located on the output side of the selector 3, a second selector portion 5 for selecting whether the data transmitted through the above data transmission routes is shifted by one bit to the left direction defined at the drawing, and output inverters 6a to 6h for inverting and driving shifted data provided from the selector portion 5 to output them in parallel.
In the same drawing, when the clock signal is at the L level, the clocked inverters 2a to 2d respectively output binary codes as receive data into the first selector portion 3 under control of the clock signal inverted to the H level through an inverter 7.
The first selector portion 3 includes N channel MOS type FET transistors (hereinafter called Nch) 8a to 8f for receiving a shift control signal S1 at each gate thereof, and other Nch 10a to 10f for receiving a signal obtained by inversion of the shift control signal S1, through an inverter 9, at each gate thereof. When the signal to be provided to each gate of the Nch is at the H level, each course between the source and the drain becomes conductible.
Moreover, the second selector portion 5 comprises Nch 11a to 11g for receiving a shift control signal S2 at each gate thereof, and other Nch 13a to 13g for receiving a signal obtained by inversion of the shift control signal S2, through an inverter 12, at each gate thereof. Similarly to the first selector portion 3, when the signal provided to each gate of the Nch is at the H level, each course between the source and the drain becomes conductible.
The pre-charge circuit 4 comprises Nch 14a to 14f for carrying out charge to the nodes N1 to N6 at a fixed positive voltage level. The Nch 14a to 14f are positioned between a power source VDD and the nodes N1 to N6.
In the above-mentioned construction, when the clock signal is at the H level as shown in FIG. 2 (time t0), since the clocked inverters 2a to 2d are controlled by the clock signal inverted at the L level through the inverter 7, data can not be received into the dynamic barrel shifter 1. In such a state, positive voltage is applied to the nodes N1 to N6 for a predetermined pre-charge period (t3-t0), at a fixed level lower than the potential of the power source voltage, by the pre-charge circuit 4, and lines on which data transmit (hereinafter called data transmission routes) provided in the first selector portion 3 and the second selector portion 5 are set at the H level (positive potential) initially. In this case, output codes OUT0 to OUT7 are inverted by the output inverters 6a to 6h, and set at the L level (zero potential).
During the pre-charging time, the potential of the input data is set (time t1), and the shift control signals S1, S2 are independently set at the H level or L level (time t2), then preparation for shifting the input data by a predetermined number of bits is carried out.
Next, when the clock signal is changed into the L level (time t3), the binary codes D0 to D3 are respectively inverted and received through the clocked inverters 2a to 2d in parallel under control of the clock signal inverted at the H level by the inverter 7.
Then, data composed of the binary codes D0 to D3 are respectively transmitted through the Nch 8c to 8f because the respective Nch 8a to 8f become conductible when the shift control signal S1 is at the H level in the first selector portion 3. Namely, the data is shifted by two bits in the left direction defined by the drawing.
When the signal S1 is at the L level, since the signal S1 is inverted into the H level by the inverter 9, the Nch 10a and 10f are in conduction, so that the data is transmitted through the Nch 10a and 10f. The data is not shifted in this case.
Then, the data is provided to the second selector portion 5, where it is selected whether the data is shifted or not. When the shift control signal S2 is at the H level, the data is transmitted through the Nch 11a to 11g. Thus, the data is shifted by one bit to the left direction in the drawing.
On the other hand, when the signal is at the L level, since the signal S2 is inverted to the H level by the inverter 12, the data is transmitted through the Nch 13a to 13g conductible. Namely, the data is not shifted.
Then, the data is transmitted through the second selector 5. Thereafter, the binary codes D0 to D3 composing the data are respectively driven by the output inverters 6a to 6g to output as the output codes OUT0 to OUT7 (time t4).
FIG. 3 shows the result of the shift of the data.
As shown in FIG. 3, when the output codes OUT0 to OUT7 corresponding to the binary codes D0 to D3 for forming the input data composed of four bits are detected, these codes are divided into an output portion I of four bits for outputting the output codes from OUT0 to OUT3 and another output portion II of four bits for outputting the output codes from OUT4 to OUT7.
By detecting these output codes by dividing them into the output portion I and the output portion II, a data shifted in the left direction is designated by the output portion I, and the shifted bit number is changed between 0 and 3. While a data shifted in the right direction is designated by the output portion II, and the shifted bit number is changed between 1 and 4.
In other words, the four-bit dynamic barrel shifter 1 can freely carry out all kinds of data shifts by controlling the shift control signals S1 and S2 to the data composed of four bits.
Next, the electric potential change of data transmission routes in the operation mode of the dynamic barrel shifter 1 is explained.
When the clocked inverters 2a to 2d are conductible and the input codes are at the H level, the input codes are respectively inverted to the L level by the clocked inverters 2a to 2d. By the inversion into the L level, all the electric power pre-charged at the transmission routes of input codes and the input sides of output inverters 6a to 6g connected to the transmission routes is discharged. Then, by the discharge, when the potential level of the data transmission routes pre-charged at a predetermined positive level in advance is decreased to a value lower than the threshold voltage (generally, a half of the power source voltage VDD) of the output inverters 6a to 6g, the output inverters 6a to 6g respectively judge that the binary codes to be transmitted are at the L level, then change the level of the output codes into the H level. The time required for shifting the input codes of the H level and outputting them is the time required for the discharge in which the potential level of the input codes is decreased from the H level to a level lower than the threshold voltage.
On the other hand, when the input codes at the L level (zero potential), the input codes are inverted at the H level (positive potential) by the clocked inverters 2a to 2d. In this case, the electric power pre-charged in advance at the transmission routes of the input codes is maintained as it is, so that the positive potential on the input sides of the respective output inverters is not changed. Since the potential level of the output codes are kept at the L level, the time required for shifting the input codes of the L level is substantially zero.
Accordingly, in such a dynamic barrel shifter for carrying out pre-charge to the data transmission routes, since the time required for processing input codes of the L level is substantially zero, the data process can be carried out far more rapidly than that in barrel shifters where the pre-charge is not carried out.
Moreover, in the dynamic barrel shifter 1 shown in FIG. 1, since the positive pre-charge voltage obtained by utilizing the back gate effect of Nch can be controlled at a value of VDD-Vth (Vth is a voltage value of about 1.7V corresponding to voltage drop by the back gate effect) lower than the power source voltage VDD (set at 5V in this case), as compared with a case where the pre-charge voltage is controlled at the same potential with the power source voltage VDD, the time required for discharge in which the pre-charge voltage is decreased to a value lower than the threshold voltage (1/2 VDD) can be shortened. Namely, since the time required for processing input codes of the H level can be shortened, the data process can be carried out much more rapidly.
However, in the dynamic barrel shifter mentioned above, since the difference between the potential level VDD-Vth of the binary codes of the H level and the threshold voltage (1/2 VDD) of the output inverters 6a to 6h is small, an operation margin of the output inverters 6a to 6h is so narrow that wrong operation is likely to be caused by charge share, noises and coupling.
To improve this, a method in which a transfer gate composed of a group of the Nch of the second selector portion 5, for example the Nch 11a and 13a as shown in FIG. 4a, is replaced with a pass transistor as shown in FIG. 4b.
Namely, the pass transistor is composed of a circuit in which a parallel circuit provided with the Nch 11a and a P channel MOS type FET transistor (hereinafter, called Pch) and another parallel circuit provided with the Nch 13a and a Pch are connected in parallel.
In the method using such a pass transistor, since the back gate effect on the Nch can be eliminated by the Pch, the electric potential of binary codes of the H level to be transmitted to the output inverters 6a to 6h from the second selector portion 5 becomes equal to the power source voltage VDD, so that a satisfactory operation margin can be obtained.
However, in the pass transistor method, the number of transistors included in the second selector portion 5 is increased twice, thus the size of the dynamic barrel shifter must be large.
Therefore, there is also considered another method in which the group of Nch included in the second selector 5 are all exchanged for a group of the Pch so as to eliminate of the back gate effect.
However, since charge and discharge ability of the Pch is inferior to that of the Nch, the operation time is increased. Moreover, the difference between the electric potential of the binary codes at the H level to be transmitted to the output inverters 6a to 6h, that is, the power source voltage VDD and the threshold voltage (1/2 VDD) of the output inverters 6a to 6h becomes large, so that the time required for discharging the potential of the data transmission routes to the threshold voltage is inevitably elongated. This means that the time required for processing the input codes at the H level increases.